The IS200BICLH1A Bridge Interface Board is a critical interface component designed by GE for its Innovation Series™ drive systems. It acts as the "nerve center" and "guardian" between the drive's main control board and various Bridge Personality Interface boards (such as the IS200BPIA, IS200BPIB, or IS200SCNV).
The board is designed for installation in a VME-type rack and interacts with the system via its two main connectors, P1 and P2. The P1 connector handles field-level signals like bridge control, fault strings, temperature monitoring, and fan control. The P2 connector manages communication, including data, address, and control signals, with the main control board and logic power supply.
A key feature of the BICL board is its high flexibility and configurability. By loading different firmware into its Electronically Programmable Logic Device (EPLD), it can adapt to two primary application scenarios: IGBT drives and SCR source bridges, demonstrating its versatile and robust design.
2. Key Functions & Features
The IS200BICLH1A board integrates several critical functions essential for the safe, reliable, and efficient operation of the drive system.
System Interface & Communication Hub: It serves as the vital link between the drive's main control board and the power unit (bridge), translating commands into control signals for the power semiconductors (IGBTs or SCRs) and reporting status and fault feedback back to the main control.
Configurable Logic Control (EPLD): The board's "brain" is an EPLD, configured by the main CPU on power-up or hard reset. Two primary configurations exist:
BICLEPLD: Used with BPIA or BPIB boards for IGBT drive applications.
SCNVEPLD: Used with the SCNV board for SCR source bridge and Dynamic Braking (DB) IGBT applications.
This programmable architecture allows a single hardware board to serve different technical platforms.
Comprehensive Fault Monitoring & Safety Protection: The BICL implements a multi-layered fault monitoring and protection network.
Fault String Inputs: It provides two independent, electrically isolated fault string inputs for Panel (Local) and System interlock contacts, supporting 24V or 115V ac/dc.
Power Device Fault Monitoring: Monitors faults such as IGBT desaturation and shunt faults (BICLEPLD) or DB IGBT faults (SCNVEPLD).
Watchdog Circuit: A hardware watchdog monitors the 20 MHz EPLD clock. If the clock fails, it disables bridge firing and drops out the contactors within 30 microseconds.
Contactor Control & Status Feedback: The board controls the MA and MB contactor pilot relays. The MA relay also controls the IGBT gate driver power and includes a MA Sense (MASEN) input to verify the main contactor has pulled in, providing a critical safety interlock.
Temperature Monitoring: The board features four Resistance Temperature Detector (RTD) analog inputs (typically for phases A, B, C, and ambient). The signals are digitized by a 10-bit, 4-channel Analog-to-Digital Converter (ADC).
Intelligent Fan Speed Control: A Pulse Width Modulation (PWM) output controls cooling fan speed. This isolated open-collector output adjusts fan speed based on the PWM duty cycle, enabling a balance between cooling performance and noise/energy consumption.
Serial Board Identification: A 1024-bit serial memory chip stores the board's identification and revision data, allowing the system to automatically identify the board for maintenance and diagnostics.
3. Working Principle
The board's operation revolves around its EPLD core, processing and responding to signals from the main control and the field.
Power-up/Reset Initialization: Upon power-up, the main CPU configures the BICL's EPLD via the P2 data and address buses, determining its operational mode (IGBT or SCR).
Normal Operation Signal Flow:
Control Downstream (Main Control -> Bridge): The main control sends commands via P2. The EPLD interprets these and generates corresponding control signals (e.g., PWM for IGBTs, gate pulses for SCRs) output via P1.
Feedback Upstream (Bridge -> Main Control): The BICL continuously acquires system status via P1, including fault signals, VCO feedback (for voltage/current), RTD temperature data, and contactor status, reporting them to the main control.
Protection Mechanism Synergy: The hardware design ensures protection response is prioritized and fast. A broken fault string will immediately disable bridge firing via hardware logic before the contactors drop out. The watchdog provides an independent hardware safety layer.
Fan Control Logic: The EPLD generates the PWM waveform, but its duty cycle is typically calculated by the main control software based on the reported temperature data, forming a closed-loop intelligent cooling system.
4. System Integration & Interfaces
The IS200BICLH1A board integrates into the system through its two large connectors.
P1 Connector (Bridge Control & Field Interface): A high-density interface whose pinout varies significantly between BPIA/BPIB and SCNV applications. It includes contactor controls, fault strings, sensor inputs, drive signals, VCO feedback, and fan PWM.
P2 Connector (Main Control Communication & Power): A standard VME-style interface for the 32-bit data bus, 14-bit address bus, control signals (chip select, read, write, reset, interrupt), power inputs, and clock signals.
5. Installation & Maintenance
Dedicated Slot: The board must be installed in Slot 5 of the VME rack. Incorrect slotting may cause malfunction or damage.
ESD Protection: The board contains static-sensitive components and must be handled with appropriate ESD precautions.
Safety: Power must be turned off and verified before installing or removing the board.
Proper Installation: Use the ejector handles and secure the board with the captive screws to ensure it is correctly seated.
