The IS200BICIH1A Bridge Interface Controller Board is a core control component designed by GE Industrial Systems for its Innovation Series™ drive systems. As a highly integrated and powerful controller, the IS200BICIH1A is primarily used to manage and control bridge inverter units that employ Integrated Gate Commutated Thyristors (IGCTs) as switching devices. The IS200BICIH1A board mounts in an Innovation Series™ standard board rack and, through precise coordination with the backplane, various signal acquisition boards, and gate drive circuits, performs real-time control, signal conditioning, and multi-dimensional protection for complex power electronic conversion systems.
The core value of the IS200BICIH1A lies in its powerful capability to control up to 28 IGCT devices, supporting the generation of three-level inverter control logic, while simultaneously controlling a diode source and the Dynamic Braking (DB) section. In terms of hardware, the IS200BICIH1A integrates multiple FPGA logic chips, a Digital Signal Processor (DSP) dedicated to co-processing, and numerous daughterboards. This establishes a layered, highly reliable system architecture, ranging from sub-microsecond fast protection to complex control algorithm co-processing.
Core Functions and Control Architecture
The IS200BICIH1A board interfaces with the IS200CABP Control Assembly Backplane Board through backplane connectors P1 and P2, enabling signal interaction with the system main controller and other peripheral boards. Input power for the IS200BICIH1A is provided by the DS200RAPA Rack Power Supply Board, supplied through the backplane. Acting as the control core, the IS200BICIH1A receives gate command and status feedback signals from the IS200BPII Bridge Power Interface Board, conditioning and forwarding these signals.
Regarding local intelligent processing, the IS200BICIH1A features an onboard Digital Signal Processor (DSP) that operates as a coprocessor for the main DSPX control board. Its boot process is centrally managed by the DSPX board: the DSPX board first loads a boot loader image into the Dual-Port RAM (DPRAM), then releases the reset signal for the IS200BICIH1A's local DSP, allowing it to begin executing code. The two processors share access to local hardware registers through a built-in arbitration mechanism within the register logic, ensuring orderly and consistent interaction for control commands and status data.
Signal Processing and High-Precision Feedback Mechanisms
The IS200BICIH1A board provides three front panel connectors – PFBK1, PFBK2, and PSRC – which serve as key interfaces for achieving high-precision signal acquisition and rapid protection.
PFBK1 and PFBK2 Connectors: These two 44-pin high-density connectors are responsible for receiving signals from the IS200GGXI Expander Load/Source Boards. PFBK1 handles feedback signals from the first full bridge or the first half of the cells in a series bridge configuration, while PFBK2 handles feedback from the optional second full bridge or the second half of the cells. Feedback signal types include phase currents, phase voltages, and DC link voltages.
PSRC Connector: This 50-pin high-density connector receives feedback signals from the IS200GGXD Expander Diode Source Board and is responsible for sending gate control signals to the Dynamic Braking (DB) IGCT switches.
Voltage Feedback Isolation: Voltage signals from the DS200NATO Voltage Feedback Scaling Board are safely isolated on the IS200BICIH1A board through attenuation.
All analog current and voltage feedback signals are transmitted differentially via shielded twisted-pair cables within shielded cables to the IS200BICIH1A. Upon entering the board, these signals are split into two parallel processing paths:
Hardware Fast Protection Path: The analog signals are directly compared against multiple programmable threshold values to generate protection logic signals for immediate hardware action, such as overcurrent protective turn-off, load fault turn-off, and current freeze fault signals.
Software High-Precision Sampling Path: Each analog feedback signal passes through a synchronous Voltage-Controlled Oscillator (VCO), linearly converting the analog voltage value into a frequency signal. The output frequency ranges linearly from 0 Hz for a full-scale negative input to 2 MHz for a full-scale positive input. These frequency signals drive counters within the BRDG_IO FPGA, which are then read by the active DSP to compute high-precision current and voltage feedback values for complex control algorithms.
Gate Command and Critical Timing Management
All gating commands issued by the IS200BICIH1A to the IGCT Gate Driver boards (IS200IGPA) are subject to hardware-enforced minimum on-time and minimum off-time restrictions to prevent damage to the costly IGCT devices. Its key gating timing management functions include:
Inner-Outer Timing: The turn-on and turn-off of outer IGCTs in a bridge leg relative to the inner IGCTs are precisely delayed according to skew times defined in the firmware.
Phase Underlap: When a phase changes its output state, the IS200BICIH1A initiates a timer that momentarily freezes all phase states until the commutation reactor has sufficient time to reset, thereby preventing dangerous phase-to-phase short circuits.
Gate Driver Fault Detection: The IS200BICIH1A continuously monitors the health status feedback from each IGCT gate driver module. If an abnormal status feedback counter overflow is detected, a fault latch is immediately set, triggering the drive system to trip.
Programmable Logic Core
The powerful core functionality of the IS200BICIH1A board is realized by its two on-board SRAM-based Field Programmable Gate Arrays (FPGAs): the BRDG_IO FPGA and the CELL_IO FPGA.
CELL_IO FPGA: This FPGA is specifically responsible for the discrete control and protection directly related to the IGCT gate drivers. It manages the precise timing of PWM cycles and executes the most critical hardware protection actions, such as responding to overcurrent or shoot-through faults by immediately turning off the affected devices and recording fault events in status registers. It contains PWM timers, initial state registers, etc. All control parameters use a double-buffered structure, allowing them to be updated within one task interval and take effect synchronously on the next load pulse.
BRDG_IO FPGA: Serving as the interface between the DSPX/local DSP and the bridge control signals, this FPGA manages all general discrete I/O, fault reporting, VCO counters, the tachometer interface, and analog I/O. Its built-in VCO counters latch count values for reading by either processor. The tachometer interface supports high-precision fractional pulse calculations. Furthermore, write access to all command registers is locked out when the Power Electronics Enable (PE_ENABLE) flag is active, preventing erroneous operations during drive operation.
Protection and Diagnostic System
The IS200BICIH1A features a multi-layered, multi-dimensional protection and diagnostic network to ensure effective safeguarding under all abnormal operating conditions.
Instantaneous Hardware Protection: Primarily executed by the CELL_IO FPGA with extremely fast response times.
Protective Turn-Off (PTO): Triggered by a load fault (latched), instantaneous overcurrent, or gate driver fault, immediately turning off the victim cell(s).
Shoot-Through Fault Protection: Detects dangerous rates of current change (di/dt) by monitoring the voltage across the DC link reactor. If the condition persists longer than the fault filter time, a major fault latch is set, initiating a freeze action for all phase units. This provides sufficient time for the fuses in the faulted phase to clear, preventing fault escalation.
Status Monitoring and Reporting: Through the BRDG_IO and CELL_IO status registers, the IS200BICIH1A reports a wide variety of fault and status information, including but not limited to: various power supply faults, clock faults, gate driver faults for all IGCTs, fuse faults, and cable connection errors.
On-Board Self-Diagnostics:
Board Identification (BRDID): The IS200BICIH1A incorporates an onboard serial PROM ID chip, with its identification network extended to the GGXI boards. A unique current direction detection mechanism ensures the correct connection of PFBK and JGATE cables, preventing cross-wiring.
Front Panel Indicator: A single IMOK LED indicator provides an intuitive visual display of the board's health status; if the LED is off, a fault condition is indicated.
Testpoints: The front panel provides a total of 8 testpoints, TP1 through TP8, which bring out key analog signals such as Phase A1/B1/C1 currents and line-to-line voltages VAB1/VBC1, as well as positive and negative DC bus voltages, for convenient on-site diagnostics.
Analog I/O: The system integrates three 12-bit analog inputs for monitoring the board's local ambient temperature, an external thermistor temperature, and performing self-test loopback of protective threshold voltages. It also has eleven analog outputs used for setting protection thresholds and providing diagnostic D/A conversion.
